1. Field of the Invention
This invention relates to electronic packaging, and particularly to a method for providing micro-C4 reliability by reducing the impact of hot spot pulsing.
2. Description of Background
An electronic package typically consists of a silicon chip (e.g., 15×15 mm) and a substrate (e.g., 40×40 mm) joined by an array of solder bumps called C4, or “controlled collapsed chip connection” (e.g., 100 μm diameter×100 μm height×200 μm pitch). An advanced electronic package may consist of multiple silicon chips assembled over a single planar silicon substrate (e.g., 40×40 mm), called a silicon carrier, which is attached to a substrate using C4s. In an advanced package, the silicon chips are attached to the silicon carrier using μ-C4s (e.g., 25 μm diameter×10 μm height×50 μm pitch).
The reliability of an electronic package is affected by the fatigue life of its solder joints. Industry testing on conventional wear-out mechanisms in an electronic packaging generally focuses on low-cycle fatigue in which an assembly is subjected to deep thermal cycles (DTC) (e.g., −55° C. to 125° C.). Solder joints are subjected to significant plastic strain under DTC. A certain amount of vibration testing is also performed in which high-cycle fatigue life is evaluated. Under high-cycle fatigue the strain levels are weak and the solder can be considered more elastic than, plastic.
Power dissipated in a microprocessor is non-uniformity distributed among its logical units, it is expected, for example, that a floating-point unit may dissipate power at a much higher density (e.g., 5× to 7×) than the rest of a microprocessor in a numerically intensive computing environment. The localized dissipation of heat at higher power densities can result in zones with substantially higher temperatures. These zones are referred to as “hot spots.” On a high performance processor (e.g., 8×12 mm) several hot spots may exist, in this description two hot spots, each (e.g., 2×2 mm) in size, is considered. These hot spots may release 20 W of thermal power each while the remaining chip is dissipating 60 W. Cooling solutions can contain, peak temperatures below a pre-selected level. Since the hot spots are utilized according to customer workload, the power dissipated in a chip is not only non-uniformity, but also varies by time. The customer workload therefore arrives for processing at random time intervals. Thus, the temperature near a hot spot is likely to fluctuate accordingly.
Steady power dissipation often results in steady temperature gradients within an electronic package. Therefore, the strain level due to coefficient of thermal expansion (CTE) mismatch and temperature gradient is also steady. Since the solder has creep properties, initial strain following a power-ON event is known to relax to a steady value after a delay in time, typically in minutes or some fraction of an hour, depending on the temperature and composition of the solder. New generation of lead-free solder tends to have low creep rate. The repetition rate of this strain cycle, which would amount to a few power-On/Off cycles per day, contributes to relatively lower strains and thus takes many cycles to induce fatigue failure. DTC testing essentially evaluates the power-On/Off life under accelerated conditions. However, when hot spots are randomly activated due to customer workload, power dissipation fluctuates.
This fluctuation, referred to as hot spot pulsing, in turn results in transient strain cycles. Hot spot pulsing conditions have likely always been in existence in electronic systems, but they have not been significant enough to trigger a new failure mode. Detailed analysis of an advanced package system reveals that, when hot spot power density is pushed more than 5× that of the average power density of a chip, substantial strain levels can occur due to temperature gradient. Furthermore, if the effect of the CTE differential, for example of an organic substrate, is included in the strain analysis, the solder strain levels caused by hot spot pulsing are likely to increase further. Since the time scale of hot spot pulsing is of the order of milliseconds, time interval needed for solder relaxation is insufficient and solder creep may not play a significant role in determining the solder fatigue failure.
Considering the above limitations, it is desired to improve the reliability of μ-C4s and C4s against hot spot driven, high cycle fatigue failure.